Configurable Design and Simulation of PCI-Express Data Link Layer Transmitter

PCI-Express is a high performance, general purpose I/O interconnect communication protocol. This paper presents the detailed implementation of configurable Data Link Layer Transmitter of PCI-Express 3.0. The proposed architecture presents the transmitter module which contains the sophisticated features of PCI-Express 3.0. It explains how TLPs are processed in data link layer transmitter by appending the next sequence number as start frame and 32-bit LCRC as end frame. Protocols of PCI-Express 3.0 like link acknowledgement time out replay mechanism, flow initialization protocol and error correction protocol have been implemented and verified. The architecture of retry buffer is also presented with all the experimental results and it also explains how the retransmission is happening in the transmitter module. At the end of the design, Linting and Synthesis have been done and analyzed timing, power and utility report.