Design of AHB Reconfigurable Master Arbiter

Select the right master, while dealing with number of master trying to sense a single data bus. The effectiveness of a system to resolve this priority resides in its ability to logical assignment of the chance to transmit data width of the data. The purpose of this paper is to propose the scheme to implement reconfigurable architecture. This scheme involves typical Advanced Microcontroller Bus Architecture (AMBA) features like “Single clock edge operation�, “non-tristate implementation�, “burst transfer�, etc. In this paper, Advanced Peripheral Bus (APB) is used to reconfigure the arbiter. In this arbiter there are some register which are reconfigured with the help of APB bus. Also there are three arbitration scheme are used for arbitration. Round robin, First Come First serve (FCFS), highest priority schemes are used. The design architecture is written using the verilog hardware description language using the Xilinx ISE tools.