A Review on Clock Gating Technique for Power Reduction in VLSI Designs |
Author(s): |
| PRERNABEN MAHESHBHAI PATEL , Darshan Institute of Technology,Rajkot; PRIYANKA S. PATEL, SVIT,VASAD |
Keywords: |
| clock gating, low power design, sequential circuit |
Abstract |
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Pulsed-latched circuits, in which latches are triggered. In today’s world, with increasing complexity of the chip, the transistor count reached over millions of transistor. Also demand for high speed performance tends to increase the clocking frequency. With the increase in clock frequency, also the switching activity in the synchronous digital design has increased largely, increasing the dynamic power dissipation due to switching. Hence it has become necessary to reduce the power losses in due to switching activity. For such reduction clock gating technique is applied, in which the clock signal is disabled during the period of inactivity. In this paper a review of present clock gating techniques is done. |
Other Details |
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Paper ID: IJSRDV2I3466 Published in: Volume : 2, Issue : 3 Publication Date: 01/06/2014 Page(s): 818-821 |
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