Design of a Single Precision Floating Point Unit in Verilog |
Author(s): |
| Akash Kumar , Galgotias University, Greater Noida; Mayank Kumar, Galgotias University,Greater Noida; Varun Kumar, Galgotias University,Greater Noida; Sushant Shama, Galgotias University,Greater Noida |
Keywords: |
| Single Precision Floating Point Unit, Verilog, Modelsim SE 6.5 |
Abstract |
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A single precision floating point unit in verilog is introduced. The novelty of a single precision floating point unit is to provide five arithmetic operations: addition, subtraction, multiplication, division, and square root. In top-down design approach, four arithmetic modules: addition/subtraction, multiplication, division, and square root are combined to form a single precision floating point unit. Each module is independent from each other. The modules are realized and validated using verilog simulation in the Modelsim SE 6.5 and synthesis using Xlinx ISE Design Suite 13.3. |
Other Details |
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Paper ID: IJSRDV2I3509 Published in: Volume : 2, Issue : 3 Publication Date: 01/06/2014 Page(s): 865-866 |
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