Configurable Design and Simulation of Synchronous Retry Buffer for PCI-Express 3.0 Data Link Layer

PCI-Express is a high performance, general purpose I/O interconnect communication protocol. This paper presents the detailed implementation of configurable, exclusive and synchronous retry buffer used in PCI-Express data link layer transmitter with control logic that manages write and read operations, generates status flags and provides optional handshake signals for interfacing with user logic. It is often used to control the flow of packets between transmitter and receiver. It also represents various flags like fifo_full, fifo_empty, fifo_ae, fifo_af, fifo_hf and err. In this way, data integrity between transmitter and receiver is maintained. RTL coding of retry buffer has been written in Verilog language and it is simulated and verified in Modelsim PE student edition tool. At the end of the design, Linting and Synthesis have been done with the help of Xilinx Vivado tool and analyzed timing, power and utility report.