FPGA Implementation of Low Power and High Speed Mixed Multiplier

In this work, a new architecture was proposed to reduce the power dissipation of Multipliers. Low power digital Multiplier is designed based on array multiplier technique mainly used to reduce the switching power dissipation, while this new architecture offers great dynamic power savings mainly in array multipliers, due to their regular interconnection scheme, it misses the reduced area and high speed advantages of tree multipliers. Therefore, mixed style architecture, using a traditional tree based technique, combined with a booth multiplier, is proposed. Implementation of all these multiplier Architectures has been carried out on Spartan3E FPGA. By evaluating the performance of these Multiplier architectures using Xilinx ISE tool suite, it has been found that while the booth multiplier technique offers the minimum dynamic power consumption, the mixed architecture reduces the partial product and high speed operations can be performed when compared to all other architectures.