Low Power SOC Design Techniques |
Author(s): |
| Patel Pratik Vishnubhai , Ganpat University, Mehsana,Gujarat; Patel Deval Rajnikant, Ganpat University, Mehsana,Gujarat; Bhavesh Soni, Ganpat University, Mehsana,Gujarat |
Keywords: |
| Static Power Dissipation, Dynamic Power Dissipation, Clock Gate, Power Gate, Multi Voltage, Multi Threshold, Substrate Biasing, Multi-bit Flip-flop. |
Abstract |
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Power is a primary consideration in many segments of today’s electronics business. The thriving market for wireless/mobile devices such as cell phones, laptop and net book, and home entertainment electronics such as set-top boxes, digital cameras and broadband modems, is driving the need for low-power and energy-efficient system-on-chip designs. Power reduction has become a vital design goal for sophisticated design applications. Power consumption in chips, especially for technology at 90nm or below, must be lowered in order to reduce the packaging, reliability, manufacturing and operational costs of these devices. In addition, energy consumption as well as the amount of power loss over time must be managed to extend the use time of battery-powered applications. So in this paper different techniques are discussed for designing of low power SoC. |
Other Details |
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Paper ID: IJSRDV2I4285 Published in: Volume : 2, Issue : 4 Publication Date: 01/07/2014 Page(s): 812-815 |
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