Descriptive Analysis of Clocked Paired Shared Flip-Flop for Low Power VLSI applications |
Author(s): |
| Surbhi Chaudhary , Ideal Institute Of Technology; Geeta Saini, Ideal Institute of Technology; Usha Sharma, JRE Group of Institutions |
Keywords: |
| Flip-Flop, Low Power VLSI Circuits, CMOS circuit. |
Abstract |
|
The power consumption in VLSI circuits has become the most important factor for considering the efficiency of a circuit. The digital systems are required to operate at very low power and needs to be modified for the same. A Digital system consists of flip flops and latches which consumes a large amount of power due to redundant transitions and clocking systems. In order to reduce the power consumption we need to use the low power flip-flops for low power VLSI digital systems. In this paper we have taken a review of the low power clock paired shared flip-flop (CPSFF) for higher performance. |
Other Details |
|
Paper ID: IJSRDV2I4373 Published in: Volume : 2, Issue : 4 Publication Date: 01/07/2014 Page(s): 864-865 |
Article Preview |
|
|
|
|
