Performance analysis of LSDCCFF at 90 nm technology |
Author(s): |
| Misbah Saad , JSS Noida; Sangeeta Mangesh, JSS Noida |
Keywords: |
| Delay, flip-flop, low-swing, power, area. |
Abstract |
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Average power consumption is a big issue in nanometer technology. With the reduction in process geometries, device density increases and threshold voltage along with oxide thickness decrease to keep pace with performance[1]. In this paper , a modified LSDCCFF[5] (Low swing differential conditional capturing flip flop) with reduced average power consumption is introduced.It operates with a low-swing sinusoidal clock by using reduced swing inverters at the clock port.. The circuits were designed and simulated in Tanner using 90 nm technology files. Average power consumption of modified circuit is reduced by 9.98% , D to Q delay is increased by 5% compared to low swing circuit. |
Other Details |
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Paper ID: IJSRDV2I4395 Published in: Volume : 2, Issue : 4 Publication Date: 01/07/2014 Page(s): 893-895 |
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