FPGA Implementation of an Integrated Vedic Multiplier Using Verilog |
Author(s): |
| Kaveri Hatti , VTU Regional office ,PG Center, Gulbarga; Dr Raju Yanamshetti, P D A C E,Gulbarga |
Keywords: |
| Microprocessors, EDA (Electronic Design Automation), Vedic Architecture, Gate Delay |
Abstract |
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An integrated Vedic multiplier is special type of multiplier architecture, based on the length of the input bits architecture selects the appropriate multiplication sutra, is proposed. Aim of the multiplication sutras is to reduce the partial products, all the partial products are generated in single step, summing of these partial products results in final product. This reveals a speedup of proposed multiplier than the conventional multiplier. |
Other Details |
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Paper ID: IJSRDV2I6127 Published in: Volume : 2, Issue : 6 Publication Date: 01/09/2014 Page(s): 177-181 |
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