Design and Analysis of a Low Power High Performance Circuit for Dynamic CMOS Logic |
Author(s): |
| Suminder Kaur , JCDMCOE; Er. Rajni, JCDMCOE |
Keywords: |
| CMOS, VLSI, PDN, VERILOG-A |
Abstract |
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Dynamic logic is highly applicable due to its high performance and fast speed. The requirement of number of transistors decreases eminently in dynamic logic as compared to the CMOS logic so it is more efficient than the CMOS logic. In this paper we have proposed a domino circuit for low power consumption and very less power delay product. The results and their comparison to the previous design are given at the end of the chapter. The chapter is divided into different sections starting from discussion about the tool and language used, after that the next section presents the proposed work and results. The last section compares the proposed design with existing designs of d-CDMFF. |
Other Details |
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Paper ID: IJSRDV2I6227 Published in: Volume : 2, Issue : 6 Publication Date: 01/09/2014 Page(s): 402-404 |
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