An Efficient Construction of Online Testable Circuits using Reversible Logic Gates |
Author(s): |
| S. Gowtham , Saveetha School of engineering, Saveetha University; K. Ganesh Kumar, Saveetha School of engineering, Saveetha University; R. Arvind, Saveetha School of engineering, Saveetha University; Y. Azain Abdul Kadhar, Saveetha School of engineering, Saveetha University; P. Dass, Saveetha School of engineering, Saveetha University |
Keywords: |
| Reversible gate, single stuck fault, testable gate |
Abstract |
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The vital for many safety critical applications is the testable fault tolerant system. Due to its less heat dissipating characteristics, the reversible logic gaining interest in the recent times. Any Boolean logic function can be implemented using reversible gates. The credential part of the paper proposes a technique to convert any reversible logic gate to a testable gate that is also reversible. The resultant reversible testable gate can detect online any single bit errors that include Single Stuck Faults and Single Event Upsets S. Karp et.al. The proposed technique is illustrated using an example that converts a reversible decoder circuit to an online testable reversible decoder circuit. |
Other Details |
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Paper ID: IJSRDV2I7184 Published in: Volume : 2, Issue : 7 Publication Date: 01/10/2014 Page(s): 684-687 |
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