An Efficient FPGA Implementation of the Advanced Encryption Standard Algorithm |
Author(s): |
| G. Mohan , Brilliant Institute of Engineering and Technology; K. Rambabu, Brilliant Institute of Engineering and Technology |
Keywords: |
| AES, FPGA, encryption, decryption, Rijndael, block cipher |
Abstract |
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A proposed FPGA-based implementation of the Advanced Encryption Standard (AES) algorithm is presented in this paper. This implementation is compared with other works to show the efficiency. The design uses an iterative looping approach with block and key size of 128 bits, lookup table implementation of S -box. This gives low complexity architecture and easily achieves low latency as well as high throughput. Simulation results, performance results are presented and compared with previous reported designs. |
Other Details |
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Paper ID: IJSRDV2I7204 Published in: Volume : 2, Issue : 7 Publication Date: 01/10/2014 Page(s): 413-417 |
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