High Speed Carryselect Adder |
Author(s): |
| G. Kishore , vidya vikas institute of technology ,jntuh ; P. Sunil kumar, vidya vikas institute of technology ,jntuh ; S. Anil kumar, vidya vikas institute of technology ,jntuh |
Keywords: |
| Delay, power dissipation, variable adders, PDP |
Abstract |
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Highly -increasing requirement for mobile and several electronic devices want the use of VLSI circuits which are highly power efficient. The most primitive arithmetic operation in processors is addition and the adder is the most highly used arithmetic component of the processor. Carry Select Adder (CSA) is one of the fastest adders and the structure of the CSA shows that there is a possibility for increasing its efficiency by reducing the power dissipation and area in the CSA. This research paper presents power and delay analysis of various adders and proposed a 32-bit CSA that is implemented using variable size of the combination of adders, thus the proposed Carry select Adder (CSA) which has minimum Delay, and less power consumption hence improving the efficiency and speed of the Carry Select Adder. |
Other Details |
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Paper ID: IJSRDV2I7237 Published in: Volume : 2, Issue : 7 Publication Date: 01/10/2014 Page(s): 574-577 |
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