A verilog based simulation methodology for estimating statistical test for the time constancy of scaling exponents power and area |
Author(s): |
| Lokeshwari Sharma, Research Scholoar , Institute of Tehcnology and Managment , Bhilwara; Dheeraj Jain, Institute of Tehcnology and Managment , Bhilwara |
Keywords: |
| Power estimation, Verilog Based Simulation Methodology, Power Theater |
Abstract |
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The low Power estimation is an important aspect in digital VLSI circuit design. The estimation includes a power dissipation of a circuit and hence this to be reduces. The power estimations are specific to a particular component of power. The process of optimization of circuits for low power, user should know the effects of design techniques on each component. There are different power dissipation methods for reduction in power component. In this paper, estimating the power like short circuit and the total power, power reduction technique and the application of different proposed technique has been presented here. Hence, it is necessary to provide the information about the effect on each of these components. |
Other Details |
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Paper ID: IJSRDV2I8025 Published in: Volume : 2, Issue : 8 Publication Date: 01/11/2014 Page(s): 56-59 |
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