Design and Verification of Area Efficient Carry Select Adder |
Author(s): |
| Siva Sankar , Vathsalya Institute of science and technology; Ch. Swathi, Vathsalya Institute of science and technology; B. Shirisha, Vathsalya Institute of science and technology |
Keywords: |
| RISC, Lopower, BEC, Carry select adder. |
Abstract |
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Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 16, 32 square - root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area. |
Other Details |
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Paper ID: IJSRDV2I8074 Published in: Volume : 2, Issue : 8 Publication Date: 01/11/2014 Page(s): 78-80 |
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