A Simplied Bit-Line Technique for Memory Optimization |
Author(s): |
| Revansiddayya , DEPARTMENT OF PG STUDIES VTU, GULBARGA; Siddarama R. Patil, PDA COLLEGE OF ENGINEERING GULBARGA |
Keywords: |
| Fan-in, fan-out, Read write memory, Bitline |
Abstract |
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High fan-in and fan-out in read-write of memory requires more area, power, and causes large propagation delay .The number of transistor counts also increases due to large fan-in and fan-out. A simplified bit line technique for power optimization of memory proposed consumes steady power, requires less number of transistors and hence reduces the propagation delay for any fan-in and fan-out of read-write memory. Adopting simplified bit line technique, we implemented 32-word 16-bits/word, 32-word 16-bits/word and so on, 1-read, 1-write ported register files in a 1.2-V/2.5V. By using this technique 2n word x m-bits/words can be achieved with steady power consumption of 2.4mW for 1.2V/2.5V, this power consumption can be further reduced to half of present level by constraining the parameters such as temperature, speed, frequency of operation etc for processing technology. |
Other Details |
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Paper ID: IJSRDV2I8087 Published in: Volume : 2, Issue : 8 Publication Date: 01/11/2014 Page(s): 49-52 |
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