Design & Implement an IP Core for Fast Addition using Quaternary Signed Digit Number System |
Author(s): |
| Raja Lavudi , Jyothishmathi College of Engineering and Technology; R.Anil kumar, Jyothishmathi College of Engineering and Technology; J.Suresh, Jyothishmathi College of Engineering and Technology; R.Gopi Reddy, Brilliant Institute of Engg & Tech |
Keywords: |
| QSD, Modelsim6.0, Microwind, Leonardo Spectrum |
Abstract |
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With the binary number system, the computation speed is limited by formation and propagation of carry especially as the number of bits increases. Using a quaternary Signed Digit number system one may perform carry free addition, borrow free subtraction and multiplication. However the QSD number system requires a different set of prime modulo based logic elements for each arithmetic operation. A carry free arithmetic operation can be achieved using a higher radix number system such as Quaternary Signed Digit (QSD). In QSD, each digit can be represented by a number from -3 to 3. Carry free addition and other operations on a large number of digits such as 64, 128, or more can be implemented with constant delay and less complexity. Design is simulated & synthesized using Modelsim6.0, Microwind and Leonardo Spectrum. |
Other Details |
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Paper ID: IJSRDV2I8173 Published in: Volume : 2, Issue : 8 Publication Date: 01/11/2014 Page(s): 222-227 |
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