An Efficient Design and FPGA Implementation of JPEG Encoder using Verilog HDL |
Author(s): |
| M.NIKHIL , BRILLIANT INSTITUTE OF ENGINEERING & TECHNOLOGY; M.AJITH RAO, BRILLIANT INSTITUTE OF ENGINEERING & TECHNOLOGY; V.ANIL KUMAR, BRILLIANT INSTITUTE OF ENGINEERING & TECHNOLOGY |
Keywords: |
| DCT, JPEG encoder, zigzag, quantization, VLC, compression ratio |
Abstract |
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Image compression is the reduction or elimination of redundancy in data representation in order to achieve reduction in storage and communication cost. For this we use the simple computational method, 2D-DCT, using two 1D-DCT performed on matrix of (8X8). The DCT is a technique that converts a signal from spatial domain to frequency domain. Here we first convert the image into minimum code units. Then 2-D DCT is applied on each block. Then further process of Quantization, Zig-Zag approach and encoding is applied on the processed data. The architecture uses 3049 slices, 2,457 LUT, 46 I/Os of Xilinx Spartan-3 XC3S1600. |
Other Details |
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Paper ID: IJSRDV2I8216 Published in: Volume : 2, Issue : 8 Publication Date: 01/11/2014 Page(s): 352-355 |
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