Design of High Speed and Low Power Veterbi Decoder for Trellis Coded Modulation Decoders |
Author(s): |
| B.GOVIND , MADHIRA INSTITUTE OF TECHNOLOGY & SCIENCE; SK.SUBHAN, MADHIRA INSTITUTE OF TECHNOLOGY & SCIENCE; D.VENKATRAMI REDDY, MADHIRA INSTITUTE OF TECHNOLOGY & SCIENCE |
Keywords: |
| viterbi decoder, VLSI, Trellis coded modulation (TCM) |
Abstract |
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It is well known that the Viterbi decoder (VD) is the dominant module determining the overall power consumption of TCM decoders. High-speed, low-power design of Viterbi decoders for trellis coded modulation (TCM) systems is presented in this paper. We propose a pre-computation architecture incorporated with -algorithm for VD, which can effectively reduce the power consumption without degrading the decoding speed much. A general solution to derive the optimal pre-computation steps is also given in the paper. Implementation result of a VD for a rate-3/4 convolutional code used in a TCM system shows that compared with the full trellis VD, the precomputation architecture reduces the power consumption by as much as 70% without performance loss, while the degradation in clock speed is negligible. |
Other Details |
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Paper ID: IJSRDV2I8236 Published in: Volume : 2, Issue : 8 Publication Date: 01/11/2014 Page(s): 359-364 |
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