A Built In Self-Test and Repair Analyser for Embedded Memories |
Author(s): |
| Jyothi M , CMR INSTITUTE OF TECHNOLOGY |
Keywords: |
| BISR, SOC technology, memory |
Abstract |
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This paper presents a survey of different algorithms to test and repair a memory. This paper explains about different built in self-test and built in self repair analysis of embedded memories. The improvement in the yield of memories plays an important role in SOC. The use of spare rows and spare columns with redundancy allocation is proven to be more promising since it gives an optimal repair rate in a single test. |
Other Details |
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Paper ID: IJSRDV3I100351 Published in: Volume : 3, Issue : 10 Publication Date: 01/01/2016 Page(s): 610-611 |
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