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A Review on designing of two stage, three stage and multistage Operational Amplifiers using nanometer scaling for CMOS

Author(s):

Anju Sharma , NRI Institute of Information Science and Technology; Lalit Jain, NRI Institute of Information Science and Technology

Keywords:

CMOS Analog Circuit, C5 Process, 2 stage CMOS Operational Amplifier, 3 stage CMOS Operational Amplifier, Stability, UGB, Device Design, CMRR, Differential Amplifier

Abstract

This paper deals with the review for design of a 2 stage and 3 stage CMOS operational amplifier, also a pad frame and analyze the effect of various parameters on the characteristics of operational amplifier, which operates at 5V power supply using 50 nm, C5 process CMOS technology. Here parameters are computed and response curves are computed between all characteristics such as Gain, PM, GBW, Slew Rate etc using AC, DC and transient characteristics of it. The operational amplifier, design is a two-stage, three-stage, multi-stage CMOS operational amplifier. The operational amplifier is designed to exhibit properties a unity gain frequency of 75-100 MHz and exhibits a gain of 77.25dB with a 60° or more phase margin. There is numerous numbers of configurations for operational amplifier exists in literature. The classification of the namely existing topologies includes single stage, two stage, three stage and multistage amplifiers. By results and reasons two stage and three stage topologies are suitable choices for low voltage and high performance applications. A pad frame design is also reviewed for all possible configurations of operational amplifier.

Other Details

Paper ID: IJSRDV3I110511
Published in: Volume : 3, Issue : 11
Publication Date: 01/02/2016
Page(s): 899-901

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