Design of High Performance 4:2 Compressor Based Multiplier |
Author(s): |
| Mrunal Mahakale , G.H.R.A.E & T NAGPUR; Ratnaprabha Jasutkar, G.H.R.A.E & T NAGPUR |
Keywords: |
| High speed multiplier, 4:2 compressors, Vedic mathematics. VHDL code |
Abstract |
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Design of High Performance 4:2 Compressor Based Multiplier is proposed, In new technology of VLSI and communication, there is a vast demand of designing high processing speed and low area. Using multiplier unit design the integral part of processor can be form, Due to this high speed multiplier architectures become the need of the day. In this project, introduces compressor based multiplier architecture based on 4:2 compressor design. In addition to that by using Vedic mathematics high speed multiplication operation and low area design can be achieve. By minimizing the number of half adders used in a multiplier will reduces the complexity of the system. |
Other Details |
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Paper ID: IJSRDV3I120678 Published in: Volume : 3, Issue : 12 Publication Date: 01/03/2016 Page(s): 860-863 |
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