Low Power Edge Trigerred Flipflop |
Author(s): |
| S. Pavithra , Sri Eshwar College of Engineering; B. Menaka Devi, Sri Eshwar College of Engineering |
Keywords: |
| Flip-flop, Edge triggered flip-flop |
Abstract |
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Flip-flops are critical timing elements in digital circuits which have a large impact on the circuit speed and power consumption. The functioning of flip-flop is the important element in determining the efficiency of the system. To reduce the power consumption in digital circuits, a low power Explicit Edge triggered Flip-flop is designed and verified. In this design, the circuit triggers at both the positive and negative edge of the clock cycle. The proposed method is designed and simulated by TANNER EDA tools. Simulation results shows that the proposed design is power efficient when the circuit triggers at the both the positive and negative edges of the clock cycle. |
Other Details |
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Paper ID: IJSRDV3I1217 Published in: Volume : 3, Issue : 1 Publication Date: 01/04/2015 Page(s): 518-520 |
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