Fault Diagnosis in Combinational Logic Circuits : A Survey |
Author(s): |
| Sarang S. Samangadkar , VelTech University, Chennai, India.; Shridhar S. Dudam, Pune Institute of Computer Technology, Pune.; Amit Kumar sinha, Veltech University, Chennai, India |
Keywords: |
| Stuck-At-Faults, Fault Diagnosis, Test Generation, PODEM, Path Sensitization, D-Algorithm, Ternary Logic Circuits |
Abstract |
|
In any circuit that comprises the logic gates, there is possibility of occurrence of failure due to revelation of faults. Traditionally, the binary logical circuits have basic fault models such as Stuck-At faults, Bridging faults, Delay faults, etc. This paper describes the survey made on the fault diagnosis methods in the combinational binary logic circuits, which can be further used to optimize for faulty ternary digital circuits which reduce the interconnection and power consumption when compared to binary in the Integrated Circuit (IC) chips. These methods consist of algorithms for the generation of input test patterns to detect the single or multiple stuck-at faults as logical faults. |
Other Details |
|
Paper ID: IJSRDV3I21010 Published in: Volume : 3, Issue : 2 Publication Date: 01/05/2015 Page(s): 2051-2055 |
Article Preview |
|
|
|
|
