NOVEL HIGH SPEED VEDIC MATHS MULTIPLIER |
Author(s): |
| P.HARISH KUMAR , TPGIT/ANNA UNIVERSITY; Prof.S.KRITHIGA, TPGIT,VELLORE - 2 |
Keywords: |
| High Speed Multiplier, Vedic Maths Multiplier, IEEE754 Floating Point |
Abstract |
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with the advent of new technology in the fields of VLSI and communication, there is also an ever growing demand for high speed processing. It is also a well-known fact that the multiplier unit forms an integral part of processor design. Due to this regard, high speed multiplier architectures become the need of the day. In this paper, a novel architecture to perform high speed multiplication using ancient Vedic maths technique is introduced. Upon comparison, the vedic maths multiplier introduced in this paper is faster than the popular conventional methods of multiplication. First vedic maths based binary multiplication is introduced and then the same technique is extended to IEEE754 single and double precision floating point multiplication. The design and experiments were carried out on a Xilinx Virtex 5 series of FPGA and the simulation and synthesis results of the design have been compared. |
Other Details |
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Paper ID: IJSRDV3I2328 Published in: Volume : 3, Issue : 2 Publication Date: 01/05/2015 Page(s): 596-602 |
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