High Performance Scalable Input Vector Monitoring Concurrent BIST Architecture

Built-in Self-Test (BIST) techniques are used to form an effective approach for VLSI circuit testing. It does not need any extra components for testing the circuit. BIST has an advantage over cost and memory storage reduction and it can test many units in parallel without disturbing the normal operation. A novel Input vector Monitoring Built in Self-Test Scheme was used to improve the testing performance. A new proposed method issued here for better performance. A functionality reduction method is used to reduce the area, power than the previous methods. Here the logic module was modified with the component reduction and also another change in application. The memory is replaced with the new processor design. A Roving STAR algorithm is used for testing. With these modifications, the functions of testing circuit have been improved using novel input vector monitoring BIST. Area overhead, concurrent test latency and power consumption are reduced and speed has also been improved.