Design and Analysis of Leakage Power Reduction Circuits for various Power Gating Architectures

The design of low power circuit has begun to be a prime concern in chip design, substantially for portable and high performance systems. Power reduction is one of the mandatory issues. Scaling the transistor size causes sub-threshold leakage currents to become a massive component of total power dissipation. Therefore, effective techniques are required to minimize leakage power. Here we are going to design the multi-mode power switches based on various modes in power gating architectures. Multi-Threshold CMOS (MTCMOS) has appeared as an effective power gating technique in which standby sub-threshold leakage is minimized by interrupting power of the idle blocks by placing of sleep transistors. We propose a dual stack and body-biasing techniques with power gated circuits. The implementation of reconfigurable architecture provides reduced power and delay. TANNER EDA tool is used to design and verify the architectures.