Low Power High Performance Conditional Pulse Triggered Flip Flop |
Author(s): |
| Anuka , Indus Institute of Engineering and Technology, Kinana, Jind; Shalley Garg, Indus Institute of Engineering and Technology, Kinana, Jind |
Keywords: |
| Flip-flop, Low Power, Conditional Pulse Triggered |
Abstract |
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In this work, a Low Power High Performance Conditional Pulse Triggered Flip Flop is proposed. The proposed design fulfills the discharging problem using the pulse generation circuit with modified delay circuit. A three-transistor inverter design is used to reduce the circuit complexity, delay and speed up the discharge along the critical path when circuit needs. Modified scheme is used different approach to provide delay in the clock (CLK). As a result, no. of transistor reduces in pulse-generation circuit and delay inverter provides lower power dissipation. All simulation results are based on using CMOS 90-nm process technology at 500MHz clock frequency. Tanner 14.1 software is used for simulation process. Its maximum power saving against signal feed through FF is up to 37.3%. |
Other Details |
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Paper ID: IJSRDV3I2630 Published in: Volume : 3, Issue : 2 Publication Date: 01/05/2015 Page(s): 908-910 |
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