Design of Reduced Complexity Power Efficient Wallace Multiplier with Energy Recovery Logic

The goal of our work is to propose a multiplier with fast estimation and less power consumption using adiabatic logic and to evaluate its performance in case of sequential circuits and effect upon cascaded stages. In our current work we have designed a more power efficient, Tree Multiplier i.e. Wallace Multiplier structure with especially power efficient Full adders designed with Energy recovery logic(Adiabatic). Main advantage of this logic is greater speed and minimum power requirement. It is preferable to the arithmetic circuits. Power consumption of full adder with adiabatic style is lesser than the full adder designed without adiabatic logic. The power consumption of Adiabatic Wallace multiplier is get reduced from Wallace tree multiplier without adiabatic logic by about 89% .We have designed the circuit on 90nm technology using Tanner EDA Tool 13.0.