Reconfigurable Architecture of CSDA-Based DCT with High Accuracy ECAT

The main objective of the project is to develop a demonstrative model for reconfigurable architecture of common sharing distributed arithmetic-based DCT with high accuracy error-compensated adder tree. DCT compresses the image using common sharing distributed arithmetic in ROM based device. In common sharing distributed arithmetic compression, the rate of throughput is low. In this project, the rate of throughput will be increased by using similarity oriented logic simplification adder tree in place of common sharing distributed arithmetic. By using similarity oriented logic simplification, power Consumption, area will be reduced efficiently, which it is reduce propagation delay and number of transistors required is reduced and increasing throughput rate in ROM based device. The advantage of similarity oriented logic simplification adder logic is that it can be implemented using very less number of adders, hence very less power dissipation. This result shows the increased rate of throughput at the range of 1GB/sec. The similarity oriented logic simplification adder tree core supporting digital cinema or ultrahigh resolution format. Using simulation in Xilinx13.2 software, the rate of similarity oriented logic simplification is inferred in order to access the incremental of throughput.