Verilog Implementation of UART with Status Register |
Author(s): |
| Sangeetham Rohini , Sri Padmavathi Mahila Viswa Vidyalam |
Keywords: |
| Universal Asynchronous Receiver Transmitter; status register; Verilog implementation; ISE simulator; asynchronous serial communication |
Abstract |
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In parallel communication the cost as well as complexity of the system increases due to simultaneous transmission of data bits on multiple wires. Serial communication overcomes this drawback and emerges as effective way in many applications for long distance communication as it reduces the signal distortion because of its simple structure. This paper focuses on the Verilog implementation of UART with status register which supports asynchronous serial communication. The paper presents the architecture of UART which indicates, during reception of data, different types of errors like parity error, framing error, overrun error and break error using status register. The whole design is functionally verified using Xilinx ISE Simulator. |
Other Details |
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Paper ID: IJSRDV3I2793 Published in: Volume : 3, Issue : 2 Publication Date: 01/05/2015 Page(s): 1961-1965 |
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