Designing of FIFO for the High Speed Memory Access

High speed is one of the most required feature for the up to date electronic systems designed for its high performance and handy applications. First-In First-Out memories (FIFOs) have advanced from objectively simple logic functions to high-speed buffers combine large blocks of Static Random Access Memory. FIFOs are often used to sensibly pass data from one clock control to another asynchronous clock control. Using a FIFO to pass data from one clock domain to another clock domain needs multi- asynchronous clock design techniques. This impression will detail one method that is used to design, synthesize and analyse a safe FIFO connecting different clock domains using Memory counter that are synchronized into a different clock domain before testing for "FIFO full" or "FIFO empty" conditions and Address Calculator that are used to read/write data in user preferred address. The demonstratively evaluated, synthesized counter and address calculator can be included in FIFO.