High Performance and Low Power Level Converting Flip-Flop for Low Power Applications

In modern digital VLSI circuits, the clock system is composed of flip-flops. The Clustered voltage scaling (CVS) is an effective way to reduce power dissipation and improve the performance in digital integrated circuits. Level converting flip-flops (LCFF) are the critical elements in the CVS scheme. And then low power level-converting flip-flop with a conditional clock technique (CC-LCFF) has been designed and the circuit is simulated in 90nm CMOS technology on Mentor Graphics tool. Along this one the clock signal will be conditionally blocked when the input data don’t make any transition, and then the internal node redundant transitions are eliminated and the total power dissipation is decreased. But the CC-LCFF design suffers from issues like long discharge path and some extra internal node switching activity. Due to this, less quantity of power is dissipated in level converting flip-flop with a conditional clock technique. To further shorten the power dissipation, a Conditional Pulse-Enhancement technique and conditional discharge technique is proposed in CCER-LCFF. The proposed techniques also reduce the length of the discharge path and internal nodes switching activity in LCFF. It will be designed in 90nm CMOS technology on Mentor Graphics tool for evaluating the power dissipated and the outcomes are compared with an existing blueprint.