Design of Digital Pulse Width Modulator with High Resolution and Optimized Power |
Author(s): |
| Girish , VTU Regional Centre, Mysuru |
Keywords: |
| Field programmable gate arrays (FPGA), power conversion, pulse-width modulated power converters |
Abstract |
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Advantages of digital control in power electronics have led to an increasing use of digital pulse-width modulators (DPWM). However, the clock frequency requirements may exceed the operational limits when the power converter switching frequency is increased, while using classical DPWM architectures. In this paper, we present two designs to increase the resolution of the DPWM signals. First architecture is asynchronous method using NAND and MUX this architecture gives higher switching frequency as well as good resolution. And second proposed architecture is based on the on-chip digital clock manager block. These architectures have been designed, tested, and verified the performance of these architectures. |
Other Details |
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Paper ID: IJSRDV3I30413 Published in: Volume : 3, Issue : 3 Publication Date: 01/06/2015 Page(s): 890-894 |
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