Modern Development Environment for Implementing Ladder Logic of Micro-PLC on FPGA

Inside the PLC base on microprocessor which is executing ladder diagram sequential. But the performance of PLC is limited by the length of program and operation speed of the microprocessor. PLC doesn’t executing parallel rung of ladder diagram concurrently. Ladder Diagram is a form of graphical language type PLC programming that represents the schematics of electrical relay circuit diagram. A new technology such as Field Programmable Gate Array (FPGA) for industrial process control applications. To enhance the performance of traditional PLC, an approach to design and develop a new micro-PLC based on FPGA. FPGA has provided optimal performance, parallel execution mechanism and hardware structure. Therefore, to convert ladder diagram into VHDL program for increase the performance of PLC. Therefore, implement GUI (Graphical User Interface) tool base on Visual Studio 2010 platform, for ladder diagram entry and then automatic convert ladder diagram to VHDL code. Synthesis and simulate generated VHDL code for micro-PLC base on FPGA. The conversion process of ladder diagram to VHDL is verify and demonstrates by simple example.