FPGA Implementation of High Speed Mux Based Adder |
Author(s): |
| Balaji K. T. , CDAC ACTS, PUNE; Shridhar Dudam, Pune Institute of Computer Technology, Pune; Kalaiarasan, Veltech University, Chennai |
Keywords: |
| Addition, Mux based adder, High Performance, Verilog Simulation, Xilinx, FPGA |
Abstract |
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Adders are one of the widely used digital components in digital integrated circuit design. In this paper, various adder structures can be used to execute addition such as serial and parallel structures and most of researches have done research on the design of high-speed, low-area, or lowpower adders. Adders like ripple carry adder, carry select adder, carry look ahead adder, carry skipadder, carry save adder exist numerous adder implementations each with good attributes and some drawbacks. This paper focuses on the implementation and simulation of 4-bit, 8-bit and 16-bit and 32 bit mux based adder based on Verilog code [3] and compared for their performance in Xilinx [1]. We have recorded the performance improvements in propagating the carry and generating the sum when compared with the traditional carry look ahead adder designed in the same technology. |
Other Details |
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Paper ID: IJSRDV3I30569 Published in: Volume : 3, Issue : 3 Publication Date: 01/06/2015 Page(s): 2205-2208 |
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