Low Power Delay Locked Loop Based Clock and Data Recovery Circuit using Standby Filter |
Author(s): |
| Satya Narayan Panda , GITAM INSTITUTE OF TECHNOLOGY AND MANAGEMENT; Ch.Raja Sekhar, GITAM INSTITUTE OF TECHNOLOGY AND MANAGEMENT |
Keywords: |
| DLL, CDR, Level Tracking, Standby Filter, One-hot multiplexer |
Abstract |
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A low power DLL based CDR circuit has been proposed in this paper. The standby filter is the new feature in this design. Level tracking is used for data recovery. VHDL is used for designing the circuit. Cadence tool is used for generating and verifying the layout. Total area of the die and total power dissipation due to switching events is 0.01mm2 and 799.8643μW respectively at 1800mV power supply. |
Other Details |
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Paper ID: IJSRDV3I30826 Published in: Volume : 3, Issue : 3 Publication Date: 01/06/2015 Page(s): 3489-3491 |
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