Design of High Speed VLSI Architecture for Quark Family |
Author(s): |
| Viji.M , Velalar College of Engineering and Technology; Nishaangeline.M, Velalar College of Engineering and Technology; Valarmathi.S, Bannari Amman Institute of Technology |
Keywords: |
| Hash Functions, Sponge Functions, Lightweight Cryptography |
Abstract |
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In this communication world, to convey thought/information, communication must be necessary. While doing this, the thought/information should be kept in a secret way. In the military application, the lag of secrecy have a chance to destroy the world too. With the help of hash function, the security can be achieved; by the same time the world can also be protected. The most common cryptographic uses hash functions. The hash functions are used for digital signatures and data integrity. A hash function is a function that takes some message of any length as input and transforms it into a fixed length output called a hash value/digest. There are many well-known hash functions; some of them include SHA-1, SHA-2 and SHA-3. SHA-3 performs the best operations than SHA-2 and SHA-1. QUARK, a family of SHA-3 is taken. It runs a sequential code in parallel on a multi-core architecture. Hence the maximum speed may be obtained. QUARK has the family of U-QUARK, D-QUARK and S-QUARK. They were differs in the value of pre-image resistance and parallelization degree. QUARK uses the sponge construction so it can be used for digital signature and message authentication. The advantage is that it is necessary to minimize the amount of hardware, the power and energy consumption. In this paper the gate-equivalents(GE) are reduced with the help of parallel processing and pipelining techniques. A hash function is said to be as lightweight, due to reduction in GE. QUARK exists by using linear feedback shift register(LFSR) and non-linear feedback shift register(NLFSR). NLFSR is more resistant to cryptanalytic attacks than LFSR. LFSR is simple and efficient but, it uses a serial architecture. Hence maximum speed is obtained for VLSI architecture. |
Other Details |
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Paper ID: IJSRDV3I30962 Published in: Volume : 3, Issue : 3 Publication Date: 01/06/2015 Page(s): 3439-3442 |
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