CMOS LECTOR Technique: A Technique for Leakage Reduction in Domino Circuits

In this work a circuit technique is proposed for lowering the subthreshold leakage energy consumption of domino logic circuits. With the advancement of technology, size of transistor, supply voltage, gate oxide thickness has been decreased but the leakage in device has increased. Projecting these trends, it can be seen that the leakage power dissipation will equal to the active power dissipation within a few generations. Hence, efficient leakage power reduction methods are very critical for the deep-submicron and nanometre circuits. In this paper Lector based Footed Diode Domino Logic circuit technique is introduced for leakage reduction, which provides efficient reduction in leakage in ideal and non ideal mode of operation. In this technique a p-type and an n-type leakage control transistor (LCT) are introduced between the pull-up and pull-down network, and the gate of one is controlled by the source of the other. For any combination of inputs, one of the LCTs will operate near its cut-off region and will increase the resistance between supply voltage and ground, resulting in reduced leakage current.