Design of Polar List Decoder using 2-Bit SC Decoding Algorithm |
Author(s): |
| V.Priya , Velalar college of engineering and technology; M.Parimaladevi, Velalar college of engineering and technology |
Keywords: |
| Polar Codes, Successive Cancellation, Polar List Decoder, 2-Bit SC Decoding Algorithm |
Abstract |
|
The number of decoding architecture techniques are introduced for wireless communication channel. Such architectural techniques aim to improve the latency, area and complexity of various methods. This paper aims to get solution for FPGA based list decoder architecture, achieving the latency, area and throughput of the system. In this paper, 2bit Successive Cancellation (SC) decoding algorithm is used in polar list decoder architecture. Also, the usage of CRC in list decoder increases the throughput. The architecture is implemented in Xilinx Spartan 3E FPGA device. The result shows that the latency is reduced up to 64% compared to conventional SC decoder. The proposed design achieves area and delay of 88% & 17.3% than conventional SC decoder. |
Other Details |
|
Paper ID: IJSRDV3I31120 Published in: Volume : 3, Issue : 3 Publication Date: 01/06/2015 Page(s): 2282-2286 |
Article Preview |
|
|
|
|
