Low Power Conditional Pulse Control Flip Flop using Signal Feed Through Scheme |
Author(s): |
| Resham Singh , YMCAUST FARIDABAD; Bal Krishan, YMCAUST FARIDABAD; Naveen Kumar Sigroha, YMCAUST FARIDABAD |
Keywords: |
| Flip-Flop; Low power; Signal feed through scheme; Conditional pulse; Transmission gate circuit; Sequential circuits; Lower power dissipation |
Abstract |
|
In the present work, Low Power Conditional Pulse Control Flip-Flop using Signal Feed through scheme is proposed. The proposed design removes the long discharging path problem with intermediate nodes using the pulse generation control (which facilitates a faster discharge operation). Transmission gate and three inverters are used to control the clock circuit to reduce the power dissipation along the critical path. As a result, very low power dissipation occurs when there is no switching. Tanner EDA tool 14.1 is used for the simulation purposes. All simulation results are based on using CMOS 90-nm technology at 500MHz clock frequency. Its maximum power saving compared to PT-FF with Pulse Enhancement Scheme FF design[1][2] is up to 26.84% and 14.72% than PT-FF with Pulse Enhancement Scheme FF design [1]. |
Other Details |
|
Paper ID: IJSRDV3I31187 Published in: Volume : 3, Issue : 3 Publication Date: 01/06/2015 Page(s): 2766-2769 |
Article Preview |
|
|
|
|
