Design of 4 Bit Array Multiplier with GDI using Low Power Adder Cells |
Author(s): |
| Spandana .M , SJBIT; Dr. Nataraj K.R, SJBIT |
Keywords: |
| Gate Diffusion Input, CMOS, Full Adder, Low power, Multiplier |
Abstract |
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GDI a new techinque of designing low power digital combinational circuits.this reduces power consumption ,transistor count,propogation delay and area of digital circuits.The main objective of this thesis is to provide new power solutions for VLSI designers. simulaion result shows that the proposed GSDI has better performance in terms of power and transistor count in comparison with cmos design. GDI proposes and compared with traditional CMOS. Comparison of GDI transistor count with CMOS is presented. . Simulation result shows that the propose GDI has better performance in terms of power consumption and transistor count in compared to CMOS design. In our paper, we designed the 4*4 array multiplier based on GDI and the simulations are performed by CADENCE VIRTUOSO based on 180nm CMOS technology. |
Other Details |
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Paper ID: IJSRDV3I31610 Published in: Volume : 3, Issue : 3 Publication Date: 01/06/2015 Page(s): 3508-3511 |
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