Design and Analysis of Low Power CMOS Charge Pump |
Author(s): |
| Sheeba S , kalaignar karunanidhi Institute of technology; A.ParimalaGandhi, kalaignar karunanidhi Institute of technology |
Keywords: |
| VLSI, PLL, Charge Pump, Voltage Level Shifter, Low Power |
Abstract |
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A new high efficiency charge pump circuit is designed and realized in 130nm CMOS process. This paper work analyses the design of various CMOS Charge pumps. The performance of charge pumps mainly depends on the ability to efficiently generate high output voltages from the low input supply voltage. The shoot through current and the switching noise are being reduced by the proposed CMOS charge pump circuit. It is also used to improve the large driving capability and for eliminating the reversion loss. The proposed cross coupled charge pump has provided up to 8% percentage efficiency as compared with the conventional CMOS charge pump. |
Other Details |
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Paper ID: IJSRDV3I40053 Published in: Volume : 3, Issue : 4 Publication Date: 01/07/2015 Page(s): 359-363 |
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