Self Bias Transistor & Transmission Gate Logic Technique: For 8:1 Multiplexer

Power dissipation and propagation delay are the contradicting factors in the design of VLSI CMOS devices .This paper aims at reducing power and energy dissipation using Transmission Gate Logic (TGL) Multiplexer CMOS circuits and Self Bias Transistor Circuits comprise of reducing the power supply voltages to investigates the performance parameters i.e. delay, power for the combinational circuit using power reduction techniques and compare them to find out the best one. These techniques can be used further for various applications in the field of VLSI design. A competitive approach is applied to the 8 Bit MUX circuit emphasizing on the minimum Power-Delay trade-off and minimum Transistor count. The PMOS and NMOS transistors are connected together for strong output level. SBT technique achieves 70% reduction of power dissipation and TGL technique achieves 83% reduction of power in active mode as compared to the conventional CMOS design. SPICE Simulations are performed with 0.18µm CMOS technology.