Built in Self Test Technique based On Three Weight Pattern Generation |
Author(s): |
| Selvamani B , TRP engineering college(SRM Group); Anandhan, TRP engineering college(SRM Group) |
Keywords: |
| Built-In-Self-Test, Concurrent Testing, On-Line, Off-Line |
Abstract |
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Built-In Self-Test (BIST) techniques are used to find solution to the difficult problem of testing VLSI systems and circuits. Key vector monitoring simultaneous BIST scheme used to avoid problems in online and in offline BIST schemes. A original key vector monitoring simultaneous BIST architecture has been presented and SRAM-cell are used to store the information of whether an key vector has appeared or not during normal operation. The proposed method is three weight pattern generation pseudorandom built-in-self-test (BIST) method to achieve complete fault coverage in BIST applications by reducing number of vectors. Weighted sets are 0, 1, and 0.5 have been used generate test pattern generation and achieve low testing time less power consumption, The proposed scheme is simulated and synthesized using Xilinx 12.1 software. |
Other Details |
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Paper ID: IJSRDV3I40537 Published in: Volume : 3, Issue : 4 Publication Date: 01/07/2015 Page(s): 822-825 |
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