1-Bit Full Subtructor using CMOS Technique & GDI Technique using Tanner EDA Tool

In this paper an area and power efficient 14T 1-bit Full Subtractor design has been presented by using GDI techniques. The 1-bit Subtractor design consist of 7 NMOS and 7 PMOS. For difference output of 1-bit full Subtractor GDI XOR-XNOR module outputs has been used with GDI 2x1 MUX. A GDI XOR- XNOR module has been used which consume less area at 180 nm as compared with the CMOS modules. To improve delay and power efficiency a cascade implementation of XOR module has been avoided in the used 1-bit GDI Full Subtractor module. Power dissipation and propagation delay are the contradicting factors in the design of VLSI CMOS devices .This paper aims at reducing power and energy dissipation using Gate Diffusion Input (GDI) 1-Bit Full Subtractor circuits and CMOS Circuits comprise of reducing the power supply voltages to investigates the performance parameters i.e. delay, power for the combinational circuit using power reduction techniques and compare them to find out the best one. These techniques can be used further for various applications in the field of VLSI design. A competitive approach is applied to the 1-Bit Full Subtractor circuit emphasizing on the minimum Power-Delay trade-off and minimum Transistor count. The PMOS and NMOS transistors are connected together for strong output level. GDI technique achieves 80% reduction of leakage current and 80% reduction of leakage power in active mode as compared to the conventional CMOS design. SPICE Simulations are performed with 0.18µm CMOS technology.