High Speed Multiplier Based On Ancient Indian Vedic Mathematics |
Author(s): |
| Vipul J. Kiyada , RK. University, Rajkot; Punit A. Lathiya, RK. University,Rajkot |
Keywords: |
| Vedic Mathematic; Vedic multiplier, Urdhva Triyagbhyam Sutra, Nikhilam Navatashcaramam Dashatah |
Abstract |
|
Multiplier is one of the key hardware component in high performance system such as Finite Impulse Response (FIR) filters and Digital Signal Processor (DSP). Multiplier consumes large chip area, long latency and consume considerable amount of power. Hence better multiplier architectures can increase the efficiency of the system. Multiplier based on Vedic mathematics is one such promising solution. For the multiplication, Urdhva Tiryagbhyam sutra and Nikhilam sutra is used from Vedic mathematics. The paper shows the design implementation and comparison of these multiplier using Verilog Hardware Description Language (HDL). The multiplier based on Urdhva Tiryagbhyam sutra reduces the execution time by maximum 58% and minimum 9% but Multiplier based on Nikhilam sutra reduces the execution time by minimum 13% compared to array multiplier and increases 87% compared to Wallace tree multiplier. |
Other Details |
|
Paper ID: IJSRDV3I40814 Published in: Volume : 3, Issue : 4 Publication Date: 01/07/2015 Page(s): 1342-1344 |
Article Preview |
|
|
|
|
