Implementation of Vedic Multiplier using VLSI |
Author(s): |
| Omkar K Patil , Maratha Mandal Engineering college,Belgaum |
Keywords: |
| Urdhva-Tiryagbyham, Vedic multiplier and sutras, Digital signal processor, Xilinx |
Abstract |
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Todays processors mostly depends on multipliers as it is the important key hardware block in processors. This paper proposed the design of 64x64 bit Vedic multiplier based on Urdhava Tiryakbhyam sutra which means vertical and crosswise. The multiplier and multiplicand each group in 32 bit which decomposes the use of 32x32 multiplication module. Further, the Verilog coding Urdhava Tiryakbhyam sutra for 64x64 Vedic multiplier have been done using Xilinx ISE 14.2 software. |
Other Details |
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Paper ID: IJSRDV3I40846 Published in: Volume : 3, Issue : 4 Publication Date: 01/07/2015 Page(s): 1694-1697 |
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