Simulation of Encoder & Decoder using HDL language and Implementation in VLSI |
Author(s): |
| Bharamana V. Dukare , Maratha Mandal Engineering college,Belgaum |
Keywords: |
| Convolution Encoders, Viterbi Decoder and Constraint Length, Forward Error Correction, Path Unit |
Abstract |
|
This work outlines the performance of the convolution Encoder and Viterbi decoder for error detection and correction. The entire system is designed using vhdl. This is widely used in Digital video and camcorder. A FEC technique is the fundamental element of wireless communication systems. The some available important standards such as Third generation (3G) systems, Global system for mobile, 802.11A, and 802.16 exert some configuration of convolution coding. Viterbi decoding with convolution encoding is a most widely used method for forward error correction. Viterbi decoder algorithm is used for decoding algorithm for convolution codes which finds error detected to the system. This paper represents the encoder and viterbi decoder is implemented for constraint length of 9 and bit rate ½.. |
Other Details |
|
Paper ID: IJSRDV3I40848 Published in: Volume : 3, Issue : 4 Publication Date: 01/07/2015 Page(s): 1643-1645 |
Article Preview |
|
|
|
|
